1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device including, for example, a non-volatile semiconductor memory device which can be electrically rewritten.
2. Description of the Related Art
As a non-volatile semiconductor memory which can be electrically rewritten, a NAND flash memory is known. The NAND flash memory comprises a memory cell transistor having a stacked gate structure in which a tunnel insulation film, a charge storage layer, an intergate insulation film, and a control gate electrode are sequentially stacked on a semiconductor substrate.
With this structure, the memory cell transistor may be degraded by an increase in electrons trapped in the tunnel insulation film caused by repeated rewriting. With a higher threshold voltage, the degraded memory cell transistor will have a higher write speed, thus increasing the possibility of an over-program condition (failure of being biased above a desired threshold voltage as a result of writing). Further, with the trapped electrons detrapped by being left at a high temperature, the degraded memory cell transistor is biased far below the threshold voltage, and thereby decreases in data retention characteristics.
A current NAND flash memory is provided with a margin for write/read setting, such that a proper operation is guaranteed even in such a degraded memory cell transistor. Set to guarantee a proper operation even in a degraded memory cell transistor, a memory cell transistor deteriorates in performance in a state where degradation is rarely found, for example, immediately after the product is shipped. Considering that there is a case where degradation of a memory cell transistor recovers by increasing the time interval of rewriting at a high temperature, the degree of degradation of a memory cell transistor after being rewritten thousands of times or several tens of thousands of times greatly varies depending on conditions.
Further, in order to guarantee data retention characteristics after being rewritten thousands of times or several tens of thousands of times, the NAND flash memory is subjected to a reliability assessment before being shipped. For example, in order to estimate the duration of a NAND flash memory, for example, hundreds of hours of reliability assessment must be performed. It is therefore very difficult to monitor reliability quickly during process change or commercial production.
As a related technique of this kind, “Jpn. Pat. Appln. KOKAI Publication No. 8-7597” discloses the technique as will be described below. After data writing/erasure to/from a memory cell transistor, verification reading is performed to verify whether the data writing/erasure has been performed properly. The data writing/erasure and the verification reading operations are repeated for a predetermined number of times until the data writing/erasure is performed properly. If the proper data writing/erasure is not performed even after the operations are performed for the predetermined number of times, it is judged that the memory cell transistor has degraded, and a redundant memory cell transistor is selected instead of the degraded memory cell transistor.